Layout Design For Improved Testability Pdf 15
Layout Design for Improved Testability Pdf 15
Layout Design for Improved Testability Pdf 15
Testability is a crucial aspect of integrated circuit (IC) design, especially for complex systems-on-chip (SOCs) that contain both analog and digital components. Testability refers to the ease and effectiveness of testing a circuit for faults and verifying its functionality. Poor testability can result in increased testing time and cost, reduced product quality and reliability, and delayed time-to-market. Therefore, design for testability (DFT) techniques are widely used to enhance the testability of ICs by adding additional circuitry or modifying the existing design to improve the controllability and observability of the circuit under test (CUT).
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One of the challenges of DFT is to minimize the area overhead and performance degradation caused by the added or modified circuitry. This requires careful consideration of the layout design of the DFT circuitry, as well as the interaction between the DFT circuitry and the original design. Layout design for improved testability is a topic that covers various aspects of DFT implementation, such as placement, routing, power distribution, signal integrity, parasitics, and manufacturability. The layout design can have a significant impact on the effectiveness and efficiency of the DFT techniques, as well as the overall quality of the IC.
This article provides an overview of some of the layout design issues and solutions for improved testability, based on a review of several research papers and books on DFT. The article focuses on three main categories of DFT techniques: ad-hoc techniques, scan design techniques, and boundary scan techniques. The article also briefly discusses some emerging DFT techniques, such as built-in self-test (BIST) and design for debug (DFD).
Ad-hoc Techniques
Ad-hoc techniques are DFT techniques that are applied to specific types of circuits or faults, without following a systematic methodology or standard. Ad-hoc techniques are usually based on the designer's intuition and experience, and may involve adding test points, multiplexers, switches, or other logic elements to improve the controllability or observability of certain nodes or signals in the CUT. Ad-hoc techniques can be effective for testing certain classes of faults or circuits, but they may not be scalable or reusable for different designs or technologies. Moreover, ad-hoc techniques may introduce additional layout challenges, such as increased area, routing congestion, power consumption, noise coupling, and process variations.
Some examples of ad-hoc techniques are:
Adding test points to increase the observability of internal nodes or signals that are difficult to access from the primary outputs. Test points are additional outputs that can be connected to internal nodes or signals through multiplexers or switches. Test points can be used to observe intermediate values during functional testing or fault diagnosis. However, test points may increase the area and routing complexity of the design, as well as introduce additional loading effects and parasitics on the original signals.
Adding multiplexers or switches to increase the controllability of internal nodes or signals that are difficult to drive from the primary inputs. Multiplexers or switches can be used to connect internal nodes or signals to external test sources, such as scan chains or boundary scan registers. Multiplexers or switches can be used to apply specific test patterns or stimuli during functional testing or fault diagnosis. However, multiplexers or switches may increase the area and routing complexity of the design, as well as introduce additional delay and noise on the original signals.
Adding logic elements to reduce the correlation or dependency between internal nodes or signals that are hard to control or observe independently. Logic elements such as inverters, buffers, XOR gates, or randomizers can be used to break feedback loops, reduce reconvergent fanouts, increase signal diversity, or introduce randomness in the CUT. Logic elements can be used to improve the fault coverage or fault isolation during functional testing or fault diagnosis. However, logic elements may increase the area and power consumption of the design, as well as alter the functionality and timing of the original signals.
Scan Design Techniques
Scan design techniques are DFT techniques that are based on a systematic methodology and standard for testing sequential circuits. Scan design techniques involve replacing some or all of the flip-flops in the CUT with scan flip-flops that can be configured into one or more scan chains. Scan chains are serial shift registers that can be used to apply test patterns to and capture test responses from the CUT in a controllable and observable manner. Scan chains can be controlled by external scan signals, such as scan enable (SE), scan input (SI), scan output (SO), and scan clock (SC). Scan design techniques can achieve high fault coverage and facilitate automatic test pattern generation (ATPG) and fault simulation for the CUT.
However, scan design techniques also introduce additional layout challenges, such as increased area, routing congestion, power consumption, clock distribution, signal integrity, and test time. Some of the layout design issues and solutions for improved testability in scan design techniques are:
Placement of scan flip-flops and scan signals. The placement of scan flip-flops and scan signals can affect the area, routing, and performance of the scan design. A good placement strategy should minimize the wirelength and congestion of the scan chains and scan signals, as well as balance the load and delay of the scan clock. Some placement techniques for scan design are:
Cluster-based placement. Cluster-based placement groups scan flip-flops into clusters based on their connectivity or proximity in the original design, and places each cluster near its corresponding logic block. Cluster-based placement can reduce the wirelength and congestion of the scan chains and scan signals, as well as preserve the functionality and timing of the original design.
Partition-based placement. Partition-based placement partitions the scan flip-flops into subsets based on their scan chain order or position, and places each subset in a separate region of the chip. Partition-based placement can reduce the wirelength and congestion of the scan chains and scan signals, as well as facilitate the routing and testing of the scan chains.
Hybrid placement. Hybrid placement combines cluster-based and partition-based placement techniques to achieve a trade-off between wirelength, congestion, functionality, timing, routing, and testing of the scan design.
Routing of scan chains and scan signals. The routing of scan chains and scan signals can affect the performance, power consumption, and signal integrity of the scan design. A good routing strategy should minimize the delay, skew, crosstalk, noise, and power dissipation of the scan chains and scan signals, as well as avoid routing conflicts or violations with the original design. Some routing techniques for scan design are:
Dedicated routing. Dedicated routing allocates separate routing resources for the scan chains and scan signals, such as dedicated metal layers or tracks. Dedicated routing can improve the performance, power consumption, and signal integrity of the scan chains and scan signals, as well as avoid routing conflicts or violations with the original design.
Shared routing. Shared routing uses common routing resources for the scan chains and scan signals with the original design, such as shared metal layers or tracks. Shared routing can reduce the area overhead and routing complexity of the scan design, but it may degrade the performance, power consumption, and signal integrity of the scan chains and scan signals, as well as cause routing conflicts or violations with the original design.
Hybrid routing. Hybrid routing combines dedicated and shared routing techniques to achieve a trade-off between area overhead, routing complexity, performance, power consumption, signal integrity, routing conflicts, and violations of the scan design.
Power distribution of scan chains and scan signals. The power distribution of scan chains and scan signals can affect the reliability and robustness of the scan design. A good power distribution strategy should provide sufficient and stable power supply for the scan chains and scan signals, as well as minimize the power noise or fluctuations caused by the switching activity of the scan chains and scan signals. Some power distribution techniques for scan design are:
Separate power network. Separate power network provides separate power supply pins or pads for the scan chains and scan signals, as well as separate power grids or rings for each scan chain or signal. Separate power network can improve the reliability and robustness of the scan chains and scan signals by isolating them from the power noise or fluctuations caused by other circuits on chip.
Shared power network. Shared power network uses common power supply pins or pads for the scan chains and scan signals with other circuits on chip, as well as shared power grids or rings for each scan chain or signal with other circuits in their vicinity. Shared power network can reduce the area overhead and pin count of the scan design, but it may degrade the reliability and robustness of the scan chains and scan signals by exposing them to the power noise or fluctuations caused by other circuits on chip.
Hybrid power network. Hybrid power network combi